Frequency divider circuits are useful in many digital circuit designs. Many conventional frequency dividers require a reset operation to ensure that the divider circuit is placed in a legal state after which it will divide as expected. Reset signals are typically synchronized with the clock signal. Accordingly, there is some level of complication when a control machine that is operating without benefit of the clock it is trying to reset must generate a clear synchronous reset signal. For high frequency clocks, the problem becomes even more complicated because the reset must occur within a period of the clock. Propagation delay through the circuit generating the reset signal is likely to be on the order of a clock period or longer for high frequency clocks. Self-initializing circuits do not require a reset signal for proper operation. There is a need, therefore, for a self-initializing frequency divider suitable for high frequency clocks.